Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles having programmable logic and programmable interconnections. These programmable tiles can include, for example, input/output blocks (“lOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3-75 through 3-96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “junction blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Transistor density of FPGAs is sufficient to allow an entire system to be within a single FPGA integrated circuit. A system may be composed of functionally discrete modules, which are interconnected to form such a system. In instances where one or more modules of a system are application-dependent or time-variant, such application-dependent or time-variant modules need not be instantiated at all times of system operation. Having application-dependent or time-variant modules being resident in a system instantiated in an FPGA not only unnecessarily consumes power and circuit resources, but also may limit the size of a system which may be implemented in an FPGA.
Accordingly, others have suggested loading a module responsive to invocation of an application associated therewith, and then removing such module once the application has completed. This type of loading and unloading of a module is known as dynamic modular partial reconfiguration, as it involves unloading of a module without turning off the power to the FPGA. A module may initially be loaded during initial configuration of an FPGA or may be loaded later. Thus, a dynamic modular system may be provided which, if all modules were implemented at the same time would exceed the number of available resources of an FPGA, but by loading and unloading modules dynamically, may be implemented on a single FPGA.
Heretofore, there were some limitations to dynamic modular partial reconfiguration, including the number of modules that could be instantiated in phases, where one module would replace another module in a row or column, without reserving the entire row or column of CLBs for such modules. Moreover, there were limitations involving routing of static routes through modules subject to replacement, such as having to recompile a design or portion thereof.
Accordingly, it would be desirable and useful to provide dynamic partial reconfiguration not limited to having to reserve an entire row or column of CLBs for such dynamic partial reconfiguration usage. Furthermore, it would be desirable and useful if static routes through modules subject to dynamic partial reconfiguration could be preserved without recompilation.